During manufacturing of integrated circuits (ICs) or during handling of such ICs, the power or ground supply nodes/pins to the ICs may experience a high supply voltage and current (e.g., several thousand volts and currents of several amperes, positive and/or negative with respect to a local ground). These high supply voltages and currents signify an electrostatic discharge (ESD) event on the nodes, and may damage the circuits coupled to the power and/or ground nodes/pins of the ICs. The power and/or ground supply nodes/pins may also experience an ESD event indirectly when other circuits coupled to the power and/or ground supply nodes/pins experience an ESD event. In such a case, the ESD on the other circuits flows through electrical paths to the power and/or ground supply nodes/pins thus causing damage to those nodes/pins and to circuits coupled to those nodes/pins. To protect these circuits, ESD protection circuits are included in the ICs to short the power supply and ground supply nodes of the IC to one another in case of an ESD event on such supply nodes.
Such ESD protection circuits protect the ICs by clamping the high or low voltage signals on the supply nodes (power supply and ground nodes). Consequently, a rapidly changing voltage (e.g., 10 mV/μS or faster) on a supply node of the IC may appear as an ESD event to the ESD protection circuit which responds to the ESD event by shorting the nodes having the supplies (power supply and ground supply) to one another to discharge the large currents (several amperes) associated with the ESD event. By discharging the large currents associated with the ESD event, buildup of high voltages on circuit nodes of the ICs is prevented.
FIG. 1 illustrates a traditional ESD protection circuit 100 having a timer unit 101 coupled to a clamp unit 102. The time constant of the timer unit 101 is selected to be shorter than the ramp time of the supply signal Vdd and longer than the duration of the ESD event. Such time constant allows the clamp unit 102 to turn on when the ESD event begins on the node having the supply signal Vdd, and to turn off after the ESD event completes on the node having the supply signal Vdd. The supply signal Vdd is generally generated by external voltage regulators (external to the IC) on the motherboard and so ESD protection is needed for such signals that are exposed external to the IC. Such external voltage regulators generally generate the supply signal Vdd with a slow ramp speed e.g., 1 mV/μS.
However, for efficient power management of ICs, advanced power generators are used that generate supply signals with fast ramp speeds (e.g., 1-10K mV/μS). These fast ramping supply signals allow the ICs to go in and out of power states to save power consumption and to improve IC performance. These fast ramping supply signals appear to an ESD protection circuit (such as the ESD protection circuit 100 of FIG. 1) as an ESD event because like an ESD event, the fast ramping supply signals ramp up or down at speeds similar or equal to a sudden high voltage spike (an ESD event) on the supply nodes of the ICs. Consequently, the ESD protection circuits (such as the ESD protection circuit 100 of FIG. 1) are unable to distinguish between a fast ramping supply signal and an ESD event on a node with the supply signal. Hence, such ESD protection circuits clamp the fast ramping supply signals used, for example, for power management of the ICs and thus disrupt power management of the ICs.